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| 32 Mbit (x8/x16) Concurrent SuperFlash SST36VF3203 / SST36VF3204 SST36VF3201C / 1602C32Mb (x8/x16) Concurrent SuperFlash Advance Information FEATURES: * Organized as 2M x16 or 4M x8 * Dual Bank Architecture for Concurrent Read/Write Operation - 32 Mbit Bottom Sector Protection (in the smaller bank) - SST36VF3203: 24 Mbit + 8 Mbit - 32 Mbit Top Sector Protection (in the smaller bank) - SST36VF3204: 8 Mbit + 24 Mbit * Single 2.7-3.6V for Read and Write Operations * Superior Reliability - Endurance: 100,000 cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 6 mA typical - Standby Current: 4 A typical - Auto Low Power Mode: 4 A typical * Hardware Sector Protection/WP# Input Pin - Protects 8 KWord in the smaller bank or, top or bottom bank for 16 Mbit+16 Mbit, by driving WP# low and unprotects by driving WP# high * Hardware Reset Pin (RST#) - Resets the internal state machine to reading array data * Byte# Pin - Selects 8-bit or 16-bit mode * Sector-Erase Capability - Uniform 2 KWord sectors * Chip-Erase Capability * Block-Erase Capability - Uniform 32 KWord blocks * Erase-Suspend / Erase-Resume Capabilities * Security ID Feature - SST: 128 bits - User: 256 Bytes * Fast Read Access Time - 70 ns * Latched Address and Data * Fast Erase and Program (typical): - Sector-Erase Time: 18 ms - Block-Erase Time: 18 ms - Chip-Erase Time: 35 ms - Program Time: 7 s * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling - Ready/Busy# pin * CMOS I/O Compatibility * Conforms to Common Flash Memory Interface (CFI) * JEDEC Standards - Flash EEPROM Pinouts and command sets * Packages Available - 48-ball TFBGA (6mm x 8mm) - 48-lead TSOP (12mm x 20mm) * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST36VF320x are 2M x16 or 4M x8 CMOS Concurrent Read/Write Flash Memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The devices write (Program or Erase) with a 2.7-3.6V power supply and conform to JEDEC standard pinouts for x8/x16 memories. Featuring high performance Word-Program, these devices provide a typical Program time of 7 sec and use the Toggle Bit, Data# Polling, or RY/BY# to detect the completion of the Program or Erase operation. To protect against inadvertent write, the devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. These devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the devices significantly improve performance and reliability, while lowering power consumption. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. CSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high-density, surface-mount requirements, these devices are offered in 48-ball TFBGA and 48-lead TSOP packages. See Figures 1 and 2 for pin assignments. Read Operation The Read operation is controlled by CE# and OE#; both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in a high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Program Operation Device Operation Memory operation functions are initiated using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. These devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the BYTE# pin. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 s. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. Auto Low Power Mode These devices also have the Auto Lower Power mode which puts them in a near standby mode within 500 ns after data has been accessed with a valid Read operation. This reduces the IDD active Read current to 4 A typically. While CE# is low, the devices exit Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Concurrent Read/Write Operation The dual bank architecture of these devices allows the Concurrent Read/Write operation whereby the user can read from one bank while programming or erasing in the other bank. For example, reading system code in one bank while updating data in the other bank. CONCURRENT READ/WRITE STATE Bank 1 Read Read Write Write No Operation No Operation Bank 2 No Operation Write Read No Operation Read Write Note: For the purposes of this table, write means to perform Blockor Sector-Erase or Program operations as applicable to the appropriate bank. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 2 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Sector- (Block-) Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a SectorErase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Sector- or Block-Erase operation are ignored except Erase-Suspend and EraseResume. See Figures 9 and 10 for timing waveforms. Erase-Suspend/Erase-Resume Operations The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode no more than 10 s after the Erase-Suspend command had been issued. (TES maximum latency equals 10 s.) Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erasesuspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. The Software ID Entry command can also be executed. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the last byte sequence. Chip-Erase Operation The devices provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the "1" state. This is useful when a device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. Any commands issued during the Chip-Erase operation are ignored. See Table 7 for the command sequence, Figure 8 for timing diagram, and Figure 22 for the flowchart. When WP# is low, any attempt to Chip-Erase will be ignored. Write Operation Status Detection These devices provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/ BY#) output pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ7), or Toggle Bit (DQ6) Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then the Write cycle has completed, otherwise the rejection is valid. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 3 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Ready/Busy# (RY/BY#) The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising edge of the final WE# pulse in the command sequence, the RY/BY# status is valid. When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress. When RY/BY# is high (Ready), the devices may be read or left in standby mode. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or CE#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of a Write operation. See Figure 7 for Toggle Bit timing diagram and Figure 20 for a flowchart. TABLE 1: WRITE OPERATION STATUS Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read From Erase Suspended Sector/Block Read From Non-Erase Suspended Sector/Block Program DQ7 DQ7# 0 1 DQ6 Toggle Toggle 1 DQ2 No Toggle Toggle Toggle RY/BY# 0 0 1 Byte/Word (BYTE#) The device includes a BYTE# pin to control whether the device data I/O pins operate x8 or x16. If the BYTE# pin is at logic "1" (VIH) the device is in x16 data configuration: all data I/0 pins DQ0-DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is at logic "0", the device is in x8 data configuration: only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The remaining data pins DQ8DQ14 are at Hi-Z, while pin DQ15 is used as the address input A-1 for the Least Significant Bit of the address bus. Data# Polling (DQ7) When the devices are in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling (DQ7) timing diagram and Figure 20 for a flowchart. Data Data Data 1 DQ7# Toggle N/A 0 T1.1 1270 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. The address must be in the bank where the operation is in progress in order to read the operation status. If the address is pointing to a different bank (not busy), the device will output array data. Data Protection The devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 4 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) These devices provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of the six-byte sequence. The devices are shipped with the Software Data Protection permanently enabled. See Table 7 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value during any SDP command sequence. Hardware Block Protection The devices provide hardware block protection which protects the outermost 8 KWord in the smaller bank or, top or bottom bank for 16 Mbit +16 Mbit. The block is protected when WP# is held low. When WP# is held low and a BlockErase command is issued to the protected black, the data in the outermost 8 KWord/16 KByte section will be protected. The rest of the block will be erased. See Tables 3 and 4 for Block-Protection location. A user can disable block protection by driving WP# high. This allows data to be erased or programmed into the protected sectors. WP# must be held high prior to issuing the Write command and remain stable until after the entire Write operation has completed. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Common Flash Memory Interface (CFI) These devices also contain the CFI information to describe the characteristics of the devices. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as the Software ID Entry command with 98H (CFI Query command) to address BKX555H in the last byte sequence. In order to enter the CFI Query mode, the system can also use the one-byte sequence with BKX55H on Address and 98H on Data Bus. See Figure 12 for CFI Entry and Read timing diagram. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the devices to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 16) and all output pins are set to High-Z. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 15). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 5 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Security ID The SST36VF320x devices offer a 136-word Security ID space. The Secure ID space is divided into two segments--one 128-bit factory programmed segment and one 128-word (256-byte) user-programmed segment. The first segment is programmed and locked at SST with a unique, 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Program command. End-of-Write status is checked by reading the toggle bits. Data# Polling is not used for Security ID End-of-Write detection. Once programming is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three-byte command sequence with Query Sec ID command (88H) at address 555H in the last byte sequence. See Figure 14 for timing diagram. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 7 for more details. address from the same bank without issuing a new Software ID Entry command. The Software ID Entry command may be written to an address within a bank that is in Read Mode or in Erase-Suspend mode. The Software ID Entry command may not be written while the device is programming or erasing in the other bank. TABLE 2: PRODUCT IDENTIFICATION Address Manufacturer's ID Device ID SST36VF3203 SST36VF3204 Note: BKX = Bank Address (A20-A18) Data 00BFH 7354H 7353H T2.1 1270 BKX0000H BKX0001H BKX0001H Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 7 for the software command code, Figure 13 for timing waveform and Figure 21 for a flowchart. Product Identification The Product Identification mode identifies the devices and manufacturer. For details, see Table 2 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 21 for the Software ID Entry command sequence flowchart. The addresses A20 and A18 indicate a bank address. When the addressed bank is switched to Product Identification mode, it is possible to read another FUNCTIONAL BLOCK DIAGRAM Memory Address Address Buffers (8 KWord / 16 KByte Sector Protection) SuperFlash Memory Bank 1 BYTE# RST# CE# WP# WE# OE# RY/BY# 1270 B01.0 SuperFlash Memory Bank 2 Control Logic I/O Buffers DQ15/A-1 - DQ0 (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 6 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 3: SST36VF3203, 2M X16 CSF BOTTOM DUAL-BANK MEMORY ORGANIZATION (1 OF 2) SST36VF3203 Block BA0 BA1 BA2 BA3 BA4 BA5 BA6 Bank 1 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 Bank 2 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 Block Size 8 KW / 16 KB 24 KW / 48 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB Address Range x8 000000H-003FFFH 004000H-00FFFFH 010000H-01FFFFH 020000H-02FFFFH 030000H-03FFFFH 040000H-04FFFFH 050000H-05FFFFH 060000H--06FFFFH 070000H--07FFFFH 080000H--08FFFFH 090000H--09FFFFH 0A0000H--0AFFFFH 0B0000H--0BFFFFH 0C0000H--0CFFFFH 0D0000H--0DFFFFH 0E0000H--0EFFFFH 0F0000H--0FFFFFH 100000H--10FFFFH 110000H--11FFFFH 120000H--12FFFFH 130000H--13FFFFH 140000H--14FFFFH 150000H--15FFFFH 160000H--16FFFFH 170000H--17FFFFH 180000H--18FFFFH 190000H--19FFFFH 1A0000H--1AFFFFH 1B0000H--1BFFFFH 1C0000H--1CFFFFH 1D0000H--1DFFFFH 1E0000H--1EFFFFH 1F0000H--1FFFFFH 200000H--20FFFFH 210000H--21FFFFH 220000H--22FFFFH 230000H--23FFFFH 240000H--24FFFFH 250000H--25FFFFH 260000H--26FFFFH 270000H--27FFFFH 280000H--28FFFFH 290000H--29FFFFH Address Range x16 000000H-001FFFH 002000H-007FFFH 008000H-00FFFFH 010000H-017FFFH 018000H-01FFFFH 020000H-027FFFH 028000H-02FFFFH 030000H-037FFFH 038000H-03FFFFH 040000H-047FFFH 048000H-04FFFFH 050000H-057FFFH 058000H-05FFFFH 060000H-067FFFH 068000H-06FFFFH 070000H-077FFFH 078000H-07FFFFH 080000H-087FFFH 088000H-08FFFFH 090000H-097FFFH 098000H-09FFFFH 0A0000H-0A7FFFH 0A8000H-0AFFFFH 0B0000H-0B7FFFH 0B8000H-0BFFFFH 0C0000H-0C7FFFH 0C8000H-0CFFFFH 0D0000H-0D7FFFH 0D8000H-0DFFFFH 0E0000H--0E7FFFH 0E8000H--0EFFFFH 0F0000H--0F7FFFH 0F8000H--0FFFFFH 100000H--107FFFH 108000H--10FFFFH 110000H--117FFFH 118000H--11FFFFH 120000H--127FFFH 128000H--12FFFFH 130000H--137FFFH 138000H--13FFFFH 140000H--147FFFH 148000H--14FFFFH (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 7 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 3: SST36VF3203, 2M X16 CSF BOTTOM DUAL-BANK MEMORY ORGANIZATION (CONTINUED) (2 OF 2) SST36VF3203 Block BA42 BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 Bank 2 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 Block Size 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB Address Range x8 2A0000H--2AFFFFH 2B0000H-2BFFFFH 2C0000H-2CFFFFH 2D0000H-2DFFFFH 2E0000H-2EFFFFH 2F0000H-2FFFFFH 300000H-30FFFFH 310000H-31FFFFH 320000H-32FFFFH 330000H-33FFFFH 340000H-34FFFFH 350000H-35FFFFH 360000H-36FFFFH 370000H-37FFFFH 380000H-38FFFFH 390000H-39FFFFH 3A0000H-3AFFFFH 3B0000H-3BFFFFH 3C0000H-3CFFFFH 3D0000H-3DFFFFH 3E0000H-3EFFFFH 3F0000H-3FFFFFH Address Range x16 150000H--157FFFH 158000H-15FFFFH 160000H-167FFFH 168000H-16FFFFH 170000H-177FFFH 178000H-17FFFFH 180000H-187FFFH 188000H-18FFFFH 190000H-197FFFH 198000H-19FFFFH 1A0000H-1A7FFFH 1A8000H-1AFFFFH 1B0000H-1B7FFFH 1B8000H-1BFFFFH 1C0000H-1C7FFFH 1C8000H-1CFFFFH 1D0000H-1D7FFFH 1D8000H-1DFFFFH 1E0000H-1E7FFFH 1E8000H-1EFFFFH 1F0000H-1F7FFFH 1F8000H-1FFFFFH T3.0 1270 (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 8 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 4: SST36VF3204, 2M X16 CSF TOP DUAL-BANK MEMORY ORGANIZATION (1 OF 2) SST36VF3204 Block BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 Bank 2 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 BA42 Block Size 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB Address Range x8 000000H-00FFFFH 010000H-01FFFFH 020000H-02FFFFH 030000H-03FFFFH 040000H-04FFFFH 050000H-05FFFFH 060000H--06FFFFH 070000H--07FFFFH 080000H--08FFFFH 090000H--09FFFFH 0A0000H--0AFFFFH 0B0000H--0BFFFFH 0C0000H--0CFFFFH 0D0000H--0DFFFFH 0E0000H--0EFFFFH 0F0000H--0FFFFFH 100000H--10FFFFH 110000H--11FFFFH 120000H--12FFFFH 130000H--13FFFFH 140000H--14FFFFH 150000H--15FFFFH 160000H--16FFFFH 170000H--17FFFFH 180000H--18FFFFH 190000H--19FFFFH 1A0000H--1AFFFFH 1B0000H--1BFFFFH 1C0000H--1CFFFFH 1D0000H--1DFFFFH 1E0000H--1EFFFFH 1F0000H--1FFFFFH 200000H--20FFFFH 210000H--21FFFFH 220000H--22FFFFH 230000H--23FFFFH 240000H--24FFFFH 250000H--25FFFFH 260000H--26FFFFH 270000H--27FFFFH 280000H--28FFFFH 290000H--29FFFFH 2A0000H--2AFFFFH Address Range x16 000000H-007FFFH 008000H-00FFFFH 010000H-017FFFH 018000H-01FFFFH 020000H-027FFFH 028000H-02FFFFH 030000H-037FFFH 038000H-03FFFFH 040000H-047FFFH 048000H-04FFFFH 050000H-057FFFH 058000H-05FFFFH 060000H-067FFFH 068000H-06FFFFH 070000H-077FFFH 078000H-07FFFFH 080000H-087FFFH 088000H-08FFFFH 090000H-097FFFH 098000H-09FFFFH 0A0000H-0A7FFFH 0A8000H-0AFFFFH 0B0000H-0B7FFFH 0B8000H-0BFFFFH 0C0000H-0C7FFFH 0C8000H-0CFFFFH 0D0000H-0D7FFFH 0D8000H-0DFFFFH 0E0000H-0E7FFFH 0E8000H-0EFFFFH 0F0000H-0F7FFFH 0F8000H-0FFFFFH 100000H-107FFFH 108000H-10FFFFH 110000H-117FFFH 118000H-11FFFFH 120000H-127FFFH 128000H-12FFFFH 130000H-137FFFH 138000H-13FFFFH 140000H-147FFFH 148000H-14FFFFH 150000H-157FFFH (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 9 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 4: SST36VF3204, 2M X16 CSF TOP DUAL-BANK MEMORY ORGANIZATION (CONTINUED) (2 OF 2) SST36VF3204 Block BA43 BA44 Bank 2 BA45 BA46 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 Bank 1 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 Block Size 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 24 KW / 48 KB 8 KW / 16 KB Address Range x8 2B0000H-2BFFFFH 2C0000H-2CFFFFH 2D0000H-2DFFFFH 2E0000H-2EFFFFH 2F0000H-2FFFFFH 300000H-30FFFFH 310000H-31FFFFH 320000H-32FFFFH 330000H-33FFFFH 340000H-34FFFFH 350000H-35FFFFH 360000H-36FFFFH 370000H-37FFFFH 380000H-38FFFFH 390000H-39FFFFH 3A0000H-3AFFFFH 3B0000H-3BFFFFH 3C0000H-3CFFFFH 3D0000H-3DFFFFH 3E0000H-3EFFFFH 3F0000H-3FBFFFH 3FC000H-3FFFFFH Address Range x16 158000H-15FFFFH 160000H-167FFFH 168000H-16FFFFH 170000H-177FFFH 178000H-17FFFFH 180000H-187FFFH 188000H-18FFFFH 190000H-197FFFH 198000H-19FFFFH 1A0000H-1A7FFFH 1A8000H-1AFFFFH 1B0000H-1B7FFFH 1B8000H-1BFFFFH 1C0000H-1C7FFFH 1C8000H-1CFFFFH 1D0000H-1D7FFFH 1D8000H-1DFFFFH 1E0000H-1E7FFFH 1E8000H-1EFFFFH 1F0000H-1F7FFFH 1F8000H-1FDFFFH 1FE000H-1FFFFFH T4.0 1270 (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 10 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TOP VIEW (balls facing down) 6 5 4 A13 A12 A14 A15 A16 BYTE# A9 A8 NOTE* VSS A10 A11 DQ7 DQ14 DQ13 DQ6 A19 DQ5 DQ12 VDD DQ4 1270 48-tfbga P1.0 WE# RST# NC 3 2 1 A7 A3 A17 A4 A6 A2 RY/BY# WP# A18 A20 DQ2 DQ10 DQ11 DQ3 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS A B C D E F G H Note* = DQ15/A-1 FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL TFBGA (6MM X 8MM) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1270 48-tsop P02.0 FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM) (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 11 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 5: PIN DESCRIPTION Symbol A20-A0 Name Address Inputs Functions To provide memory addresses. During Sector-Erase and Hardware Sector Protection, A20-A11 address lines will select the sector. During Block-Erase A20-A15 address lines will select the block. To output data during Read cycles and receive input data during Write cycles Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. DQ15 is used as data I/O pin when in x16 mode (BYTE# = "1") A-1 is used as the LSB address pin when in x8 mode (BYTE# = "0") To activate the device when CE# is low. To gate the data output buffers To control the Write operations To reset and return the device to Read mode To output the status of a Program or Erase operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or Program operation. To provide 2.7-3.6V power supply voltage Unconnected pins T5.0 1270 DQ14-DQ0 Data Input/Output DQ15/A-1 CE# OE# WE# RST# RY/BY# Data Input/Output and LBS Address Chip Enable Output Enable Write Enable Hardware Reset Ready/Busy# WP# BYTE# VDD VSS NC Write Protect Word/Byte Configuration To select 8-bit or 16-bit mode. Power Supply Ground No Connection TABLE 6: OPERATION MODES SELECTION DQ15-DQ8 Mode Read Program Erase CE# OE# WE# VIL VIL VIL VIL VIH VIH VIH VIL VIL RST# VIH VIH VIH DQ7-DQ0 DOUT DIN X1 BYTE# = VIH DOUT DIN X BYTE# = VIL DQ14-DQ8 = High Z DQ15 = A-1 High Z Address AIN AIN Sector or Block address, 555H for Chip-Erase X X X Standby Write Inhibit Product Identification Software Mode Reset VIHC X X X VIL X X X VIH VIHC VIH VIH High Z High Z / DOUT High Z / DOUT High Z High Z / DOUT High Z / DOUT High Z High Z High Z VIL VIL VIH VIH Manufacturer's ID (BFH) Device ID2 High Z Manufacturer's ID (00H) Device ID2 High Z High Z High Z High Z See Table 7 X X X VIL X T6.1 1270 1. X can be VIL or VIH, but no other value. 2. Device ID = SST36VF3203 = 7354H, SST36VF3204 = 7353H (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 12 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 7: SOFTWARE COMMAND SEQUENCE Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID5 User Security ID Word-Program User Security ID Program Lock-out7 Software ID Entry8,9 CFI Query Entry9 CFI Query Entry9 Software ID Exit/ CFI Exit/ Sec ID Exit10,11 Software ID Exit/ CFI Exit/ Sec ID Exit10,11 1st Bus Write Cycle Addr1 555H 555H 555H 555H XXXH XXXH 555H 555H 555H 555H 555H BKX4 55H 555H 2nd Bus Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH 3rd Bus Write Cycle Addr1 555H 555H 555H 555H 4th Bus Write Cycle Addr1 WA3 555H 555H 555H 5th Bus Write Cycle Addr1 2AAH 2AAH 2AAH 6th Bus Write Cycle Addr1 SAX4 BAX 4 Data2 AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH 98H AAH Data2 55H 55H 55H 55H Data2 A0H 80H 80H 80H Data2 Data AAH AAH AAH Data2 55H 55H 55H Data2 50H 30H 10H 555H 2AAH 2AAH 2AAH 2AAH 2AAH 55H 55H 55H 55H 55H 555H 555H 555H BKX4 555H BKX4 555H 88H A5H 85H 90H 98H SIWA6 XXXH Data 0000H 2AAH 55H 555H F0H XXH F0H T7.1 1270 1. Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value (unless otherwise stated), for the command sequence when in x16 mode. When in x8 mode, Addresses A20-A12, Address A-1, and DQ14-DQ8 can be VIL or VIH, but no other value (unless otherwise stated), for the command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence 3. WA = Program word address 4. SAX for Sector-Erase; uses A20-A11 address lines BAX for Block-Erase; uses A20-A15 address lines BKX for Bank Address; uses A20-A18 address lines 5. For SST36VF3203 the Security ID Address Range is: (x16 mode) = 100000H to 100087H,(x8 mode) = 100000H to 10010FH SST ID is read at Address Range(x16 mode) = 100000H to 100007H (x8 mode) = 100000H to 10000FH User ID is read at Address Range(x16 mode) = 100008H to 100087H (x8 mode) = 100010H to 10010FH Lock status is read at Address 1000FFH (x16) or 1001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0. For SST36VF3204 the Security ID Address Range is:(x16 mode) = 000000H to 000087H, (x8 mode) = 000000H to 00010FH SST ID is read at Address Range (x16 mode) = 000000H to 000007H (x8 mode) = 000000H to 00000FH User ID is read at Address Range (x16 mode) = 000008H to 000087H (x8 mode) = 000010H to 00010FH Lock Status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0 6. SIWA = Valid Word addresses for user Sec ID For SST36VF3203 User ID valid Address Range is (x16 mode) = 100008H-100087H (x8 mode) = 100010H-10010FH. For SST36VF3204 User ID valid Address Range is (x16 mode) = 000008H-000087H (x8 mode) = 000010H-00010FH. All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode. 7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH). 8. The device does not remain in Software Product Identification mode if powered down. 9. A20, A19, and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode With A17-A1 = 0;SST Manufacturer's ID = 00BFH, is read with A0 = 0 SST36VF3203 Device ID = 7354H, is read with A0 = 1 SST36VF3204 Device ID = 7353H, is read with A0 = 1 10. Both Software ID Exit operations are equivalent 11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the User Sec ID mode again (the programmed "0" bits cannot be reversed to "1"). (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 13 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 8: CFI QUERY IDENTIFICATION STRING1 Address x16 Mode 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Address x8 Mode 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H Data2 0051H 0052H 0059H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Description Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T8.1 1270 1. Refer to CFI publication 100 for more details. 2. In x8 mode, only the lower byte of data is output. TABLE 9: SYSTEM INTERFACE INFORMATION Address x16 Mode 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Address x8 Mode 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH Data1 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Description VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min (00H = no VPP pin) VPP max (00H = no VPP pin) Typical time out for Program 2N s (24 = 16 s) Typical time out for min size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (26 = 64 ms) Maximum time out for Program 2N times typical (21 x 24 = 32 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) T9.0 1270 1. In x8 mode, only the lower byte of data is output. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 14 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 10: DEVICE GEOMETRY INFORMATION Address x16 Mode 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Address x8 Mode 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H Data1 0016H 0002H 0000H 0000H 0000H 0002H 003FH 0000H 0000H 0001H 00FFH 0003H 0010H 0000H Description Device size = 2N Bytes (16H = 22; 222 = 4 MByte) Flash Device Interface description; 0002H = x8/x16 asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 63 + 1 = 64 blocks (003FH = 63) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) T10.2 1270 1. In x8 mode, only the lower byte of data is output. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 15 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. OPERATING RANGE Range Extended Industrial Ambient Temp -20C to +85C -40C to +85C VDD 2.7-3.6V 2.7-3.6V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 17 and 18 (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 16 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 11: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V Limits Symbol IDD1 Parameter Active VDD Current Read Program and Erase Concurrent Read/Write ISB IALP Standby VDD Current Auto Low Power VDD Current 5 MHz 1 MHz 5 MHz 1 MHz 15 4 30 45 35 20 20 mA mA mA mA mA A A CE#=VIL, WE#=OE#=VIH CE#=WE#=VIL, OE#=VIH CE#=VIL, OE#=VIH CE#, RST#=VDD0.3V CE#=0.1V, VDD=VDD Max WE#=VDD-0.1V Address inputs=0.1V or VDD-0.1V RST#=GND VIN =GND to VDD, VDD=VDD Max WP#=GND to VDD, VDD=VDD Max RST#=GND to VDD, VDD=VDD Max VOUT =GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min T11.1 1270 Freq Min Max Units Test Conditions IRT ILI ILIW ILO VIL VILC VIH VIHC VOL VOH Reset VDD Current Input Leakage Current Input Leakage Current on WP# pin and RST# pin Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD VDD-0.3 20 1 10 1 0.8 0.3 VDD+0.3 VDD+0.3 0.2 A A A A V V V V V V 1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 17) TABLE 12: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ 1 Parameter Power-up to Read Operation Power-up to Write Operation Minimum 100 100 Units s s T12.0 1270 TPU-WRITE1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: CAPACITANCE (TA = 25C, f=1 Mhz, other pins open) Parameter CI/O1 CIN 1 Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 10 pF 10 pF T13.0 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 14: RELIABILITY CHARACTERISTICS Symbol NEND TDR1 ILTH1 1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T14.0 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 17 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information AC CHARACTERISTICS TABLE 15: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR 1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Pin Low to Read Mode Min 70 Max 70 70 30 Units ns ns ns ns ns ns 0 0 16 16 0 500 50 20 ns ns ns ns ns s T15.1 1270 TRY1,2 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. TABLE 16: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH1 TIDA TSE TBE TSCE TES TBY1,2 TBR1 1 Parameter Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase Erase-Suspend Latency RY/BY# Delay Time Bus Recovery Time Min 0 40 0 0 0 10 40 40 30 30 30 0 Max 10 Units s ns ns ns ns ns ns ns ns ns ns ns ns 150 25 25 50 10 90 0 ns ms ms ms s ns s T16.1 1270 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 18 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TRC ADDRESSES TAA TCE CE# TOE OE# VIH WE# TCLZ TOH DATA VALID TCHZ HIGH-Z DATA VALID 1270 F03.0 TOLZ TOHZ DQ15-0 HIGH-Z FIGURE 3: READ CYCLE TIMING DIAGRAM TBP ADDRESSES 555 TAH TWP WE# TAS OE# TCH CE# TCS RY/BY# TDS TDH DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. VALID 1270 F04.0 2AA 555 ADDR TWPH TBY TBR FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 19 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TBP ADDRESSES 555 TAH TCP CE# TAS OE# TCH WE# TCS RY/BY# TDS TDH DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. VALID 1270 F05.0 2AA 555 ADDR TCPH TBY TBR FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS TCE CE# TOEH OE# TOE WE# TBY RY/BY# TOES DQ7 DATA DATA# DATA# DATA 1270 F06.0 FIGURE 6: DATA# POLLING TIMING DIAGRAM (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 20 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information ADDRESSES TCE CE# TOEH OE# TOE WE# TBR DQ6 TWO READ CYCLES WITH SAME OUTPUTS VALID DATA 1270 F07.0 FIGURE 7: TOGGLE BIT TIMING DIAGRAM SIX-BYTE CODE FOR CHIP-ERASE ADDRESSES 555 2AA 555 555 2AA 555 TSCE CE# OE# TWP WE# TBY RY/BY# TBR DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID 1270 F08.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 16) X can be VIL or VIH, but no other value. FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 21 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information SIX-BYTE CODE FOR BLOCK-ERASE ADDRESSES 555 2AA 555 555 2AA BAX TBE CE# OE# TWP WE# TBY RY/BY# TBR DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 VALID 1270 F09.0 Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 16) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE ADDRESSES 555 2AA 555 555 2AA SAX TSE CE# OE# TWP WE# TBR TBY RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 1270 F10.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 16) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 22 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESSES 555 2AA 555 0000 0001 CE# OE# TWP WE# TWPH DQ15-0 XXAA XX55 XX90 TAA 00BF Device ID 1270 F11.0 TIDA Device ID = 7354H for SST36VF3203 and 7353H for SST36VF3204 Note: X can be VIL or VIH, but no other value. FIGURE 11: SOFTWARE ID ENTRY AND READ THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESSES 555 2AA 555 CE# OE# TWP WE# TWPH DQ15-0 XXAA XX55 XX98 1270 F12.0 TIDA TAA Note: X can be VIL or VIH, but no other value. FIGURE 12: CFI ENTRY AND READ (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 23 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESSES 555 2AA 555 DQ15-0 XXAA XX55 XXF0 TIDA CE# OE# TWP WE# TWPH 1270 F13.0 Note: X can be VIL or VIH, but no other value. FIGURE 13: SOFTWARE ID EXIT/CFI EXIT THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS AMS-0 555 2AA 555 CE# OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX88 SW2 1270 F14.0 TIDA TAA Note: AMS = Most significant address AMS = A20 for SST39VF3203/3204 WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence X can be VIL or VIH, but no other value. FIGURE 14: SEC ID ENTRY (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 24 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information RY/BY# 0V RST# TRP CE#/OE# TRHR 1270 F15.0 FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS) TRY RY/BY# RST# TRP CE# OE# 1270 F16.0 TBR FIGURE 16: RST# TIMING DIAGRAM (DURING SECTOR- OR BLOCK-ERASE OPERATION) (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 25 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1270 F17.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1270 F18.0 FIGURE 18: A TEST LOAD EXAMPLE (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 26 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Address/Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1270 F19.0 Note: X can be VIL or VIH, but no other value. FIGURE 19: WORD-PROGRAM ALGORITHM (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 27 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Internal Timer Program/Erase Initiated Toggle Bit Program/Erase Initiated Data# Polling Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read byte/word Read DQ7 Program/Erase Completed Read same byte/word No Is DQ7 = true data? Yes No Does DQ6 match? Yes Program/Erase Completed Program/Erase Completed 1270 F20.0 FIGURE 20: WAIT OPTIONS (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 28 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Software Product ID Entry Command Sequence Load data: XXAAH Address: 555H CFI Query Entry Command Sequence Load data: XXAAH Address: 555H Software ID Exit/ CFI Exit/Sec ID Command Sequence Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX90H Address: 555H Load data: XX98H Address: 555H Load data: XXF0H Address: 555H Wait TIDA Wait TIDA Wait TIDA Read Software ID Read CFI data Return to normal operation X can be VIL or VIH, but no other value 1270 F20.0 FIGURE 21: SOFTWARE PRODUCT ID/CFI/SEC ID ENTRY COMMAND FLOWCHARTS (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 29 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information Chip-Erase Command Sequence Load data: XXAAH Address: 555H Sector-Erase Command Sequence Load data: XXAAH Address: 555H Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX50H Address: SAX Load data: XX30H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1270 F22.0 Note: X can be VIL or VIH, but no other value. FIGURE 22: ERASE COMMAND SEQUENCE (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 30 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information PRODUCT ORDERING INFORMATION SST 36 XX VF XX 320x - 70 XXXX - XXX 4E XX - B3K - XXX E X Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls or leads Package Type B3 = TFBGA (6mm x 8mm) E =TSOP (type 1, die up, 12mm x 20mm) Temperature Range E = Extended = -20C to +85C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Bank Split 3 = Bottom 24 Mbit + 8 Mbit 4 = Top 8 Mbit + 24 Mbit Device Density 320 = 1 Mbit x16 or 2 Mbit x8 Voltage V = 2.7-3.6V Product Series 36 = Concurrent SuperFlash 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST36VF3203 SST36VF3203-70-4E-B3KE SST36VF3203-70-4I-B3KE SST36VF3203-70-4E-EKE SST36VF3203-70-4I-EKE Valid combinations for SST36VF3204 SST36VF3204-70-4E-B3KE SST36VF3204-70-4I-B3KE SST36VF3204-70-4E-EKE SST36VF3204-70-4I-EKE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 31 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information PACKAGING DIAGRAMS TOP VIEW 8.00 0.20 BOTTOM VIEW 5.60 0.80 0.45 0.05 (48X) 6 5 4 3 2 1 0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20 6 5 4 3 2 1 SIDE VIEW 1.10 0.10 A1 CORNER SEATING PLANE 0.35 0.05 0.12 1mm Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4 48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM SST PACKAGE CODE: B3K (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 32 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information 1.05 0.95 Pin # 1 Identifier 0.50 BSC 12.20 11.80 0.27 0.17 18.50 18.30 0.15 0.05 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50 1mm 48-tsop-EK-8 48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 33 32 Mbit Concurrent SuperFlash SST36VF3203 / SST36VF3204 Advance Information TABLE 17: REVISION HISTORY Number 00 01 Description Date Feb 2005 Sep 2005 * * * * * * * Initial release of data sheet Updated "Erase-Suspend/Erase-Resume Operations" on page 3 Updated footnote 5 and added footnote 7 to Table 7 on page 13 Updated CFI Query Identification in Table 8 on page 14 Updated Device Geometry Information in Table 10 on page 15 Updated TES parameter from 20 s to 10 s in Table 16 on page 18 In "Product Ordering Information" on page 31 - Removed all MPNs for packages containing Pb (B3K/EK) - Removed all commercial temperature MPNs - Added extended temperature MPNs for all devices Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2005 Silicon Storage Technology, Inc. S71270-01-000 9/05 34 |
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